[AKD4691-A] 2007/06 - 1 - general description the akd4691 is an evaluation board for the ak4691, 16bit 4ch adc + 2ch dac with built-in mic/headphone/speaker amplifier. the akd4691 can evaluate a/d converter and d/a converter separately in addition to loop-back mode (a/d d/a). the akd4691 also has the digital audio interface and can achieve the interf ace with digital audio sy stems via opt-connector. ? ordering guide AKD4691-A --- evaluation board for ak4691 (cable for connecting with printer port of ib m-at compatible pc and control software are packed with this. this control software does not operate on windows nt.) function ? dit/dir with optical input/output ? 10pin header for digital audio i/f ? rca connector for an external clock input ? 10pin header for serial control i/f control i/f 10pin header 5v ak4114 opt in ak4691 avdd svdd mic2 lin/rin 1 0 3 5 1 0 3 5 dvdd mic1/beep digital audio i/f 10pin header 1 0 3 5 avdd gnd reg 3.0 v rout lout spp spn opt out 1 0 3 5 spk jack tvdd mvdd svdd lvdd dvdd tvdd1 tvdd2 dir dit mvdd hpl hpr hp jack figure 1. akd4691 block diagram * circuit diagram and pcb layout are attached at the end of this manual. evaluation board rev.0 for ak4691 a kd4691- a
[AKD4691-A] 2007/06 - 2 - ? operation sequence (1) set up the power supply lines. (1-1) in case of using the regulator. set up the jumper pins. jp2 jp3 jp4 jp5 jp6 jp7 jp8 jp reg svdd-sel avdd-sel dvdd-sel tvdd-sel vcc-sel mvdd-sel state short short short short short short short set up the power supply lines. [5v] (red) = 5.0v : for lvdd of ak4691 (typ. 5.0v) for regulator (3.0v output : svdd, mvdd, avdd, dvdd, tvdd1 and tvdd2 of ak4691 and logic) [d3v] (orange) = 2.7 3.6v : for ak4114 and logic (typ. 3.3v) [agnd] (black) = 0v : for analog ground [dgnd] (black) = 0v : for logic ground (1-2) in case of using the power supply connectors. set up the jumper pins. jp2 jp3 jp4 jp5 jp6 jp7 jp8 jp reg svdd-sel avdd-sel dvdd-sel tvdd-sel vcc-sel mvdd-sel state open open open open open open open set up the power supply lines. [5v] (red) = 2.6 ~ 5.5v : for lvdd of ak4691 (typ. 3.0v) [svdd] (orange) = 2.6 ~ 3.6v : for svdd of ak4691 (typ. 3.0v) [mvdd] (orange) = 2.6 ~ 5.5v : for mvdd of ak4691 (typ. 3.0v) [avdd] (orange) = 2.6 ~ 3.6v : for avdd of ak4691 (typ. 3.0v) [dvdd] (orange) = 2.6 ~ 3.6v : for dvdd of ak4691 (typ. 3.0v) [tvdd] (orange) = 1.6 ~ 3.6v : for tvdd1, tvdd2 of ak4691 (typ. 3.0v) [vcc] (orange) = 1.6 3.6v : for logic (typ. 3.0v: this voltage must be same as tvdd.) [d3v] (orange) = 2.7 3.6v : for ak4114 and logic (typ. 3.3v) [agnd] (black) = 0v : for analog ground [dgnd] (black) = 0v : for logic ground * each supply line should be distributed from the power supply unit. (2) set up the evaluation mode, jumper pins and dip switch. (see the followings.) (3) power on. the ak4691 and ak4114 should be resets once bringi ng sw1 (pdn) and sw2 (dir) ?l? upon power-up.
[AKD4691-A] 2007/06 - 3 - ? evaluation mode in case of the ak4691 evaluation using the ak4114, it is necessary to correspond to audio interface format for the ak4691 and ak4114. about the ak4691?s audio interface format, refer to datasheet of the ak4691. about the ak4114?s audio interface format, refer to table 2. the ak4114 operates at fs of 32khz or more. if the fs is slower than 32khz, please use other mode. in addition, mclk of ak4114 supports 256fs and 512fs. when evaluate it in a condition except this, please use other mode. about the setup of the ak4691?s register, refer to datasheet of the ak4691. applicable evaluation mode (1) evaluation of a/d using dit of ak4114. (1-1) setting with external slave mode (2) evaluation of d/a using dir of ak4114. (2-1) setting with external slave mode (3) evaluation of a/d, d/a using port3 (dsp). (3-1) setting with pll master mode (3-2) setting with pll slave mode (3-3) setting with external slave mode (4) evaluation of loop-back. (4-1) setting with pll master mode (4-2) setting with pll slave mode (4-3) setting with external slave mode
[AKD4691-A] 2007/06 - 4 - (1) evaluation of a/d using dit of ak4114. (1-1) setting with external slave mode x1 (x?tal) and port2 (dit) are used. nothing should be connected to port1 (dir) and port3 (dsp). jp23 (m/s) should be set to ?slave?. in addition, the re gister of ak4691 should be set to ?ext slave mode?. mcki, bick and lrck are supplied from ak4114, and sdto1 or sdto2 of the ak4691 is output to the ak4114. the jumper pins should be set as the following. jp15 mclk jp18 bick_sel jp19 phase 4040 dir inv thr jp21 lrck_sel 4040 dir dir ext xtl jp22 4114_mcki jp31 xte jp106 sdto sdto1 sdto2 * when sdto2 data is output to port2 (dit), jp106 should be set to ?sdto2?. tdm mode is not supported in this mode. (2) evaluation of d/a using dir of ak4114. (2-1) setting with external slave mode port1 (dir) is used. nothing should be connected to port2 (dit) and port3 (dsp). jp23 (m/s) should be set to ?slave?. in addition, the register of ak4691 should be set to ?ext slave mode?. the jumper pins should be set as the following. jp15 mclk jp18 bick_sel jp19 phase 4040 dir inv thr jp21 lrck_sel 4040 dir dir ext xtl jp22 4114_mcki jp24 sdti_sel adc dir jp31 xte
[AKD4691-A] 2007/06 - 5 - (3) evaluation of a/d, d/a using port3 (dsp). port3 (dsp) is used. nothing should be connected to port1 (dir) and port2 (dit). (3-1) setting with pll master mode the master clock is input from mcki of port3 (dsp). an internal pll circuit generates mcko, bick, and lrck. jp23 (m/s) should be set to ?master?. in addition, the register of ak4691 should be set to ?pll master mode?. sdti, sdto, lrck and bick of port 3 are respectively connected with sd to, sdti, lrck and bick of dsp. when mcko is supplied to dsp, test pin (mcko) should be directly connected to dsp. loop-filter of pll should be pr operly selected. because resist or and capacitor values are 10k ? and 4.7uf respectively on this board. ak4691 dsp or p mcko bick lrck sdto1/2 sdti bclk lrck sdti1/2 sdto mcki 1fs 32fs, 64fs 256fs/128fs/64fs/32fs 11.2896mhz, 12mhz, 12.288mhz 13.5mhz, 24mhz, 27mhz mclk figure 2. pll master mode the jumper pins should be set as the following. jp15 mclk jp19 phase inv thr jp21 lrck_sel 4040 dir jp24 sdti_sel adc dir dir ext xtl jp31 xte jp106 sdto sdto1 sdto2 * when sdto2 data is output to port3 (dsp), jp106 should be set to ?sdto2?.
[AKD4691-A] 2007/06 - 6 - (3-2) setting with pll slave mode a reference clock of pll is selected among the input clocks supplied from port3 (dsp) to mcki, bick or lrck pin. the required clock to the ak4691 is generated by an internal pll circuit. jp23 (m/s) should be set to ?slave?. (3-2-1) pll reference clock: mcki pin the register of ak4691 should be set to ?pll slave mode? (reference clock: mcki). bick and lrck inputs should be synchronized with mcko output. but the phase between mcko and lrck dose not matter. loop-filter of pll should be pr operly selected. because resist or and capacitor values are 10k ? and 4.7uf respectively on this board. ak4691 dsp or p mcko bick lrck sdto1/2 sdti bclk lrck sdti1/2 sdto mcki 1fs 32fs 11.2896mhz, 12mhz, 12.288mhz 13.5mhz, 24mhz, 27mhz mclk 256fs/128fs/64fs/32fs figure 3. pll slave mode 1 (pll reference clock: mcki pin) the jumper pins should be set as the following. jp15 mclk jp19 phase inv thr jp21 lrck_sel 4040 dir jp24 sdti_sel adc dir dir ext xtl jp31 xte jp106 sdto sdto1 sdto2 * when sdto2 data is output to port3 (dsp), jp106 should be set to ?sdto2?.
[AKD4691-A] 2007/06 - 7 - (3-2-2) pll reference clock: bick or lrck pin the register of ak4691 should be set to ?pll slave mode? (reference clock = bick or lrck). loop-filter of pll should be pr operly selected. because resist or and capacitor values are 10k ? and 4.7uf respectively on this board. ak4691 dsp or p mcki bick lrck sdto1/2 sdti bclk lrck sdti1/2 sdto mcko 1fs 32fs, 64fs figure 4. pll slave mode 2(pll reference clock: bick or lrck pin) the jumper pins should be set as the following. jp15 mclk jp14 ext jp19 phase inv thr jp21 lrck_sel 4040 dir jp24 sdti_sel adc dir dir ext xtl jp31 xte jp106 sdto sdto1 sdto2 * when sdto2 data is output to port3 (dsp), jp106 should be set to ?sdto2?.
[AKD4691-A] 2007/06 - 8 - (3-3) setting with external slave mode mclk, bick, lrck, and sdti are input from port3 (dsp). jp23 (m/s) should be set to ?slave?. in addition, the register of ak4691 should be set to ?ext slave mode?. ak4691 dsp or p mcki bick lrck sdto1/2 sdti bclk lrck sdti1/2 sdto mcko 1fs 32fs mclk 256fs, 512fs or 1024fs figure 5. ext slave mode the jumper pins should be set as the following. jp15 mclk jp19 phase inv thr jp21 lrck_sel 4040 dir jp24 sdti_sel adc dir dir ext xtl jp31 xte jp106 sdto sdto1 sdto2 * when sdto2 data is output to port3 (dsp), jp106 should be set to ?sdto2?. (4) evaluation of loop-back. (4-1) setting with pll master mode nothing should be connected to port1 (dir), port2 (dit) and port3 (dsp). jp23 (m/s) should be set to ?master? . in addition, the register of ak4691 should be set to ?pll master mode?. (4-1-1) in case of supplying mclk from j11 (ext) loop-filter of pll should be pr operly selected. because resist or and capacitor values are 10k ? and 4.7uf respectively on this board. the jumper pins should be set as the following. jp15 mclk jp14 ext jp19 phase inv thr jp21 lrck_sel 4040 dir jp24 sdti_sel adc dir dir ext xtl jp31 xte
[AKD4691-A] 2007/06 - 9 - jp106 sdto sdto1 sdto2 * when a termination (51 ? ) is not used, jp14 (ext) should be open. when sdto2 data is looped back to sdti, jp106 should be set to ?sdto2?. (4-1-2) in case of supplying mcki from x2 (11.2896mhz) the jumper pins should be set as the following. jp15 mclk jp19 phase inv thr jp21 lrck_sel 4040 dir jp24 sdti_sel adc dir dir ext xtl jp31 xte jp106 sdto sdto1 sdto2 * when sdto2 data is looped back to sdti, jp106 should be set to ?sdto2?. (4-2) setting with pll slave mode bick and lrck are generated from mcko of ak4691 on board divider. the generated bick and lrck is input to the ak4691. jp23 (m/s) should be set to ?slave?. in addition, the register of ak4691 should be set to ?pll master mode? (reference clock: mcki). nothing should be connected to port1 (dir), port2 (dit) and port3 (dsp). (4-2-1) in case of supplying mclk from j11 (ext) the jumper pins should be set as the following. jp15 mclk jp14 ext jp19 phase inv thr jp21 lrck_sel 4040 dir jp24 sdti_sel adc dir dir ext xtl jp31 xte jp18 bick_sel 4040 dir jp16 mkfs 512fs1024fs 256fs mcko jp17 bgfs 64fs 32fs jp108 mcko jp106 sdto sdto1 sdto2 *when a termination (51 ? ) is not used, jp14 (ext) should be open. when sdto2 data is looped back to sdti, jp106 should be set to ?sdto2?.
[AKD4691-A] 2007/06 - 10 - (4-2-2) in case of supplying mcki from x2 (11.2896mhz) the jumper pins should be set as the following. jp15 mclk jp19 phase inv thr jp21 lrck_sel 4040 dir jp24 sdti_sel adc dir dir ext xtl jp31 xte jp18 bick_sel 4040 dir jp16 mkfs 512fs 1024fs 256fs mcko jp17 bgfs 64fs 32fs jp108 mcko jp106 sdto sdto1 sdto2 * when sdto2 data is looped back to sdti, jp106 should be set to ?sdto2?. (4-3) setting with external slave mode jp23 (m/s) should be set to ?slave?. in addition, the register of ak4691 should be set to ?ext slave mode?. nothing should be connected to port1 (dir), port2 (dit) and port3 (dsp). (4-3-1) in case of using clocks from ak4114 x1 (12.288mhz) is used. the jumper pins should be set as the following. jp15 mclk jp18 bick_sel jp19 phase 4040 dir inv thr jp21 lrck_sel 4040 dir dir ext xtl jp22 4114_mcki jp24 sdti_sel adc dir jp31 xte jp106 sdto sdto1 sdto2 * when sdto2 data is looped back to sdti, jp106 should be set to ?sdto2?.
[AKD4691-A] 2007/06 - 11 - (4-3-2) in case of using the clock divider on the board ? in case of supplying mclk from j11 (ext) (e.g. mclk=256fs, bick=64fs) the jumper pins should be set as the following. jp15 mclk jp14 ext jp19 phase inv thr jp21 lrck_sel 4040 dir jp24 sdti_sel adc dir dir ext xtl jp31 xte jp18 bick_sel 4040 dir jp16 mkfs 512fs1024fs 256fs mcko jp17 bgfs 64fs 32fs jp106 sdto sdto1 sdto2 * when a termination (51 ? ) is not used, jp14 (ext) should be open. when sdto2 data is looped back to sdti, jp106 should be set to ?sdto2?. ? in case of supplying mcki from x2 (11.2896mhz) the jumper pins should be set as the following. jp15 mclk jp19 phase inv thr jp21 lrck_sel 4040 dir jp24 sdti_sel adc dir dir ext xtl jp31 xte jp18 bick_sel 4040 dir jp16 mkfs 512fs 1024fs 256fs mcko jp17 bgfs 64fs 32fs jp106 sdto sdto1 sdto2 * when sdto2 data is looped back to sdti, jp106 should be set to ?sdto2?.
[AKD4691-A] 2007/06 - 12 - ? dip switch set up [s1] (sw dip-6): mode setting for ak4691 and ak4114. no. name on (?h?) off (?l?) default 1 dif2 on 2 dif1 off 3 dif0 ak4114 audio format setting see table 2 off 4 ocks1 ak4114 master clock setting : see table 3 off 5 cad0 ak4691control mode setting : see table 4 off 6 mute mute normal operation off table 1. mode setting for ak4691 and ak4114 lrck bick mode dif2 dif1 dif0 daux sdto i/o i/o 0 0 0 0 24bit, left justified 16bit, right justified h/l o 64fs o 1 0 0 1 24bit, left justified 18bit, right justified h/l o 64fs o 2 0 1 0 24bit, left justified 20bit, right justified h/l o 64fs o 3 0 1 1 24bit, left justified 24bit, right justified h/l o 64fs o 4 1 0 0 24bit, left justified 24bit, left justified h/l o 64fs o default 5 1 0 1 24bit, i 2 s 24bit, i 2 s l/h o 64fs o 6 1 1 0 24bit, left justified 24bit, left justified h/l i 64 -128fs i 7 1 1 1 24bit, i 2 s 24bit, i 2 s l/h i 64 -128fs i table 2. setting for ak4114 audio interface format ocks1 mcko1 x?tal 0 256fs 256fs 1 512fs 512fs default table 3. setting for ak4114 master clock
[AKD4691-A] 2007/06 - 13 - ? jumper pins set up main board [jp1] (gnd): analog ground and digital ground open: separated. short: common. (the connector ?dgnd? can be open.) [jp2] (reg): selection of reg open: reg is not used. short: reg is used. [jp3] (svdd-sel): svdd of the ak4691 open: svdd is supplied from ?svdd? jack. short: svdd is supplied from the regulator (?svdd? jack should be open). [jp4] (avdd-sel): avdd of the ak4691 open: avdd is supplied from ?avdd? jack. short: avdd is supplied from the regulator (?avdd? jack should be open). [jp5] (dvdd-sel): dvdd of the ak4691 open: dvdd is supplied from ?dvdd? jack. short: dvdd is supplied from ?avdd? (? dvdd? jack should be open). [jp6] (tvdd-sel): tvdd of the ak4691 open: tvdd is supplied from ?tvdd? jack. short: tvdd is supplied from ?dvdd? (? tvdd? jack should be open). [jp7] (vcc-sel): vcc of the ak4691 open: vcc is supplied from ?vcc? jack. short: vcc is supplied from ?tvdd? (?vcc? jack should be open). [jp8] (mvdd-sel): mvdd of the ak4691 open: mvdd is supplied from ?mvdd? jack. short: mvdd is supplied from ? avdd? (?mvdd? jack should be open). [jp16] (mkfs): mclk frequency 256fs: 256fs. 512fs: 512fs. 1024fs: 1024fs. mcko: mcko is used. [jp17] (bcfs): bick frequency 32fs: 32fs. 64fs: 64fs. [jp22] (4114-mcki): ak4114 clock source open: x?tal of ak4114 is used. short: mcko of the ak4691 is supplied to the ak4114.
[AKD4691-A] 2007/06 - 14 - sub board [jp106] (sdto-sel): selection of sdto output sdto1: sdto1 is output. sdto2: sdto2 is output. [jp107] (tvdd2): tvdd2 of the ak4691 short: tvdd2 is supplied from tvdd. [jp108] (mcko): selection of mcko output open: mcko is not used. short: mcko is used.
[AKD4691-A] 2007/06 - 15 - ? the function of the toggle sw *upper-side is ?h? and lower-side is ?l?. [sw1] (pdn): power down of ak4691. keep ?h? during normal operation. [sw2] (dir): power down of ak4114. keep ?h? during normal operation. keep ?l? when ak4114 is not used. ? indication for led [led1] (erf): monitor int0 pin of the ak4114. led turns on when some error has occurred to ak4114. ? serial control the akd4691 can be connected via the printer port (parallel port) of ibm-at compatible pc. connect port4 (ctrl) with pc by 10 wire flat cable packed with the akd4691. tabl e 4 shows switch and jumper settings for serial control. 3-wire mode should be selected in table4. connect csn cclk/scl cdti/sda 10pin header 10pin connector 10 wire flat cable pc akd4691 sda(ack) port4 figure 6. connect of 10 wire flat cable s1 jp25 jp109 mode cad0 ctrl-sel i2c 3-wire off 3-wire open default cad=0 off i2c cad=1 on i2c short table 4. control mode setting
[AKD4691-A] 2007/06 - 16 - ? analog input/output circuits (1) input circuits r3 (short) extr2 intr2 jp30 r2-sel r1 (short) intl2 intr1 extr1 extl2 intl1 extl1 r4 (open) intr1 extr1 r2 (open) intr2 extr2 6 4 3 j3 lin/rin beep rin lin + c13 1u intl2 extl2 intl1 extl1 + c14 1u jp29 l2-sel 6 4 3 j2 mic2 jp27 l1-sel r23 20k + c12 1u 6 4 3 j1 mic1/beep beep jp28 r1-sel figure 7. intl1/intr1, intl2/intr2, extl1/extr1, extl2/extr2, beep, lin/rin input circuits (1-1) intl1/intr1 input circuit intl1/intr1 is input from j1. jp27 and jp28 should be set as the following. when the mic power is not used, jp101 and jp103 should be set to open. jp101 intl1 jp27 l1-sel jp28 r1-sel intl1 extl1 beep intr1 extr1 jp103 intr1
[AKD4691-A] 2007/06 - 17 - (1-2) intl2/intr2 input circuit intl2/intr2 is input from j2. jp29 and jp30 should be set as the following. when the mic power is not used, jp102 and jp104 should be set to open. jp102 intl2 jp29 l2-sel jp30 r2-sel intl2 extl2 intr2 extr2 jp104 intr2 (1-3) extl1/extr1 input circuit extl1/extr1 is input from j1. jp27 and jp28 should be set as the following. jp27 l1-sel jp28 r1-sel intl1 extl1 beep intr1 extr1 (1-4) extl2/extr2 input circuit extl2/extr2 is input from j2. jp29 and jp30 should be set as the following. jp29 l2-sel jp30 r2-sel intl2 extl2 intr2 extr2 (1-5) beep input circuit beep is input from j1. jp27 should be set as the following. jp27 l1-sel intl1 extl1 beep (1-6) lin/rin input circuit lin/rin is input from j3.
[AKD4691-A] 2007/06 - 18 - (2) output circuits (2-1) lout/rout output circuit r16 20k 1 2 3 4 5 j6 rout jp10 lout-sel + c33 1u 1 2 3 4 5 j5 lout jp11 rout-sel + c34 1u r14 20k rout lout r13 220 rca rca 3.5st 3.5st r15 220 6 4 3 j9 hp/lin e figure 8. lout/rout output circuit (2-1-1) in case that lout /rout is output from j5 and j6. jp10 lout_sel 3.5st rca jp11 rout_sel rc a 3.5st (2-1-2) in case that lout/rout is output from j9. jp10 lout-sel 3.5st rca jp11 rout-sel rc a 3.5st * j9 is shared with hpl/hpr. when lout/rout is output from j9, jp12 and jp13 should be set to ?rca?.
[AKD4691-A] 2007/06 - 19 - (2-2) hpl/hpr output circuit r22 10 c15 0.22u jp13 hpr r18 16 jp12 hpl + c36 220u + c35 220u 1 2 3 4 5 j8 hpr 1 2 3 4 5 j7 hpl r19 (short) r17 (short) r20 16 hpl hpr r21 10 c16 0.22u hp rca hp rca 6 4 3 j9 hp/lin e figure 9 . hpl/hpr output circuit (2-2-1) in case that hpl/hpr is output from j7 and j8. jp12 hpl hp rca jp13 hpr rc a hp (2-2-2) in case that hpl/hpr is output from j9. jp12 hpl hp rca jp13 hpr rc a hp * j9 is shared with lout/rout. when hpl/hpr is output from j9, jp10 and jp11 should be set to ?rca?.
[AKD4691-A] 2007/06 - 20 - (2-3) spp/spn output circuit 6 4 3 j10 spk jp26 spk spn spp figure 10 . spp/spn output circuit spp/spn is output from j10. jp 26 should be set as the following. jp26 spk * akemd assumes no responsibility for the troubl e when using the above circuit examples.
[AKD4691-A] 2007/06 - 21 - control software manual ? set-up of evaluation board and control software 1. set up the akd4691 according to previous term. 2. connect ibm-at compatible pc with akd4691 by 10-line type flat cable (packed with akd4691). take care of the direction of 10pin header. (please install the driver in the cd-rom when this control software is used on windows 2000/xp. please refer ?installation manual of control software driver by akm device control software?. in case of windows95/98/me, this installation is not n eeded. this control software does not operate on windows nt.) 3. insert the cd-rom labeled ?ak4691 evaluation kit? into the cd-rom drive. 4. access the cd-rom drive and double-click the icon of ?akd4691.exe? to set up the control program. 5. then please evaluate acco rding to the follows. ? operation flow keep the following flow. 1. set up the control program acco rding to explanation above. 2. click ?port reset? button. 3. click ?write default? button ? explanation of each buttons 1. [port reset] : set up the usb interface boa rd (akdusbif-a) when using the board. 2. [write default] : initialize the register of ak4691. 3. [all write] : write all registers that is currently displayed. 4. [all read] : read all registers that is currently displayed. 5. [function1] : dialog to write data by keyboard operation. 6. [function2] : dialog to write data by keyboard operation. 7. [function3] : the sequence of register setting can be set and executed. 8. [function4] : the sequence that is created on [function3] can be assigned to buttons and executed. 9. [function5] : the register setting th at is created by [save] function on main window can be assigned to buttons and executed. 10. [save] : save the current register setting. 11. [open] : write the saved values to all register. 12. [write] : dialog to write data by mouse operation. 13. [read] : dialog to read data by mouse operation. 14. [filter] : set programmable filter (fil1, fil3, eq) of ak4691 easily. ? indication of data input data is indicated on the register map. red letter indicates ?h? or ?1? and blue one indicates ?l? or ?0?. blank is the part that is not defined in the datasheet.
[AKD4691-A] 2007/06 - 22 - ? explanation of each dialog 1. [write dialog] : dialog to write data by mouse operation there are dialogs corres ponding to each register. click the [write] button corresponding to each register to se t up the dialog. if you check the check box, data becomes ?h? or ?1?. if not, ?l? or ?0?. if you want to write the input data to ak4691, click [ok] button. if not, click [cancel] button. 2. [function1 dialog] : dialog to write data by keyboard operation address box: input registers address in 2 figures of hexadecimal. data box: input registers data in 2 figures of hexadecimal. if you want to write the input data to ak4691, click [ok] button. if not, click [cancel] button. 3. [function2 dialog] : dialog to evaluate volume there are dialogs corresponding to register of 0ah, 0bh, 0ch and 0dh. address box: input registers address in 2 figures of hexadecimal. start data box: input starts data in 2 figures of hexadecimal. end data box: input end data in 2 figures of hexadecimal. interval box: data is wr itten to ak4691 by this interval. step box: data changes by this step. mode select box: if you check this check box, data reaches end data, and returns to start data. [example] start data = 00, end data = 09 data flow: 00 01 02 03 04 05 06 07 08 09 09 08 07 06 05 04 03 02 01 00 if you do not check this check box, data reaches end data, but does not re turn to start data. [example] start data = 00, end data = 09 data flow: 00 01 02 03 04 05 06 07 08 09 if you want to write the input data to ak4691, click [ok] button. if not, click [cancel] button.
[AKD4691-A] 2007/06 - 23 - 4. [save] and [open] 4-1. [save] all of current register setting values displayed on the main window are saved to the file. the extension of file name is ?akr?. (1) click [save] button. (2) set the file name and click [save] button. the extension of file name is ?akr?. 4-2. [open] the register setting values saved by [save] are written to the ak4691. the file type is the same as [save]. (1) click [open] button. (2) select the file (*.ak r) and click [open] button.
[AKD4691-A] 2007/06 - 24 - 5. [function3 dialog] the sequence of register setting can be set and executed. (1) click [f3] button. (2) set the control sequence. set the address, data and interval time. set ?-1? to th e address of the step where the sequence should be paused. (3) click [start] button. then this sequence is executed. the sequence is paused at the step of interval="-1". click [start] button, the sequence restarts from the paused step. this sequence can be saved and opened by [save] and [open] button on the function3 window. the extension of file name is ?aks?. figure 11. [f3] window
[AKD4691-A] 2007/06 - 25 - 6. [function4 dialog] the sequence file (*.aks) saved by [function3] can be listed up to 10 files, assigned to buttons and then executed. when [f4] button is clicked, the window as shown in figure 12 opens. figure 12. [f4] window
[AKD4691-A] 2007/06 - 26 - 6-1. [open] buttons on left side and [start] buttons (1) click [open] button and select the se quence file (*.aks) saved by [function3]. the sequence file name is displayed as shown in figure 13. ( in case that the selected sequence file name is ?dac_stereo_on.aks?) figure 13. [f4] window (2) (2) click [start] button, then the sequence is executed. 6-2. [save] and [open] buttons on right side [save] : the name assign of sequence file displayed on [func tion4] window can be saved to the file. the file name is ?*.ak4?. [open] : the name assign of sequence file(*.ak4) saved by [save] is loaded. 6-3. note (1) this function doesn't support the pause function of sequence function. (2) all files used by [save] and [open] function on right side need to be in the same folder. (3) when the sequence is changed in [function3], the sequence file (*.aks) should be loaded again in order to reflect the change.
[AKD4691-A] 2007/06 - 27 - 7. [function5 dialog] the register setting file(*.akr) saved by [save] function on main window can be listed up to 10 files, assigned to buttons and then executed. when [f5] button is clicked, the window as shown in figure 14 opens. figure 14. [f5] window 7-1. [open] buttons on left side and [write] button (1) click [open] button and select the register setting file (*.akr). the register setting file name is displayed as shown in figure 15. (in case that the selected file name is ?dac_output.akr?) (2) click [write] button, then the register setting is executed.
[AKD4691-A] 2007/06 - 28 - figure 15. [f5] window (2) 7-2. [save] and [open] buttons on right side [save] : the name assign of register setting file displaye d on [function5] window can be saved to the file. the file name is ?*.ak5?. [open] : the name assign of register setting file(*.ak5) saved by [save] is loaded. 7-3. note (1) all files used by [save] and [open] function on right side need to be in the same folder. (2) when the register setting is changed by [save] button on the main window, the register setting file (*.akr) should be loaded again in order to reflect the change.
[AKD4691-A] 2007/06 - 29 - 8. [filter dialog] this dialog can calculate of a coefficient of digital programmable filter (fil1, fil3 and eq), write to a register and check frequency response. window as shown in figure 16 opens when push a [filter] button. figure 16. [filter] window 8-1. setting of a parameter (1) please set a parameter of each filter. [sampling rate] ? input value of sampling frequency [unit: hz] [fil1a cut off frequency] ? input value of cut off frequency of fil1a [unit: hz] [fil3a cut off frequency] ? input value of cut off frequency of fil3a [unit: hz] [fil3a gain] ? input value of gain of fil3 a (0~-10db) [unit: db] [eqa pole frequency] ? input value of pole frequency of eqa [unit: hz] [eqa zero-point frequency] ? input value of zero frequency of eqa [unit: hz] [eqa gain] ? input value of gain of eqa (+12~0db) [unit: db] [fil1b cut off frequency] ? input value of cut off frequency of fil1b [unit: hz] [fil3b cut off frequency] ? input value of cut off frequency of fil3b [unit: hz] [fil3b gain] ? input value of gain of fil3 b (0~-10db) [unit: db] [eqb pole frequency] ? input value of pole frequency of eqb [unit: hz] [eqb zero-point frequency] ? input value of zero frequency of eqb [unit: hz] [eqb gain] ? input value of gain of eqb (+12~0db) [unit: db] (2) please set a filter type of fil1 and fil3. select ?lpf? or ?hpf? from [filter type] of fil1a, fil3a, fil1b and fil3b. (3) please set on/off of ?fil1a?, ?fil3a?, ?eqa?, ?fil1b?, ?fil3b?, ?eqb? with a check button. when checked it, the filter becomes on.
[AKD4691-A] 2007/06 - 30 - 8-2. a calculation of a register a register value is displayed when push a [register setting] button. when a value out of a setting range is set, error message is displayed, and, a calculation of register setting is not carried out. figure 17. a register setting calculation result when it is as follows that a register value is updated. (1) when [register setting] button was pushed. (2) when [f response] button was pushed. (3) when [update] button on a frequency characteristic indication window was pushed.
[AKD4691-A] 2007/06 - 31 - 8-3.indication of a frequency characteristic a frequency characteristic is displayed after a [frequency respons e] button is pushed. a register value is also updated. after "frequency range" is changed and a [update] butt on is pushed , indication of a frequency characteristic is updated. figure 18. a frequency characteristic indication result when it is as follows that a register value is updated. (1) when [register setting] button was pushed. (2) when [f response] button was pushed. (3) when [update] button on a frequency characteristic indication window was pushed.
[AKD4691-A] 2007/06 - 32 - measurement result [measurement condition] ~ measurement unit : audio precision, system two cascade ~ mcki : 256fs (12.288mhz) ~ bick : 64fs ~ fs : 48khz ~ bit : 16bit ~ measurement mode : ext slave mode ~ power supply : avdd=dvdd= mvdd=lvdd=svdd=tvdd1=tvdd2=3.0v ~ input frequency : 1khz ~ measurement frequency : 20 ~ 20khz ~ temperature : room [measurement results] 1. adc1 result lch rch unit adc: lin/rin ? adc1, ivol=0db s/(n+d) (-1dbfs) 89.8 90.2 db dr (-60dbfs, a-weighted) 94.5 94.5 db s/n (a-weighted) 94.6 94.6 db 2. adc2 result lch rch unit intl2/intr2 ? adc2, pre-amp gain=+24db, ivol=+29.625db s/(n+d) (-1dbfs) 87.5 86.5 db dr ivol=0db, (-60dbfs, a-weighted) 62.1 62.2 db s/n (a-weighted) 62.1 62.2 db 3. dac result lch rch unit dac: dac ? lout/rout, ivol= dvol=lvol=0db, rl=10k ? s/(n+d) (0dbfs) 86.2 86.1 db dr (-60dbfs, a-weighted) 89.5 89.6 db s/n (a-weighted) 90.2 90.2 db headphone-amp: dac ? hpl/hpr, ivol=dvol=0db, rl=22.8 ? , hpg bit = ?0? s/(n+d) (-3dbfs) 72.5 72.2 db dr (-60dbfs, a-weighted) 89.5 89.4 db s/n (a-weighted) 90.3 90.3 db speaker-amp: dac ? spp/spn, ivol=dvol=0db, rl=8 ? s/(n+d) spkg=+10.65db, (-3dbfs) 61.3 db s/n (a-weighted) 89.7 db
[AKD4691-A] 2007/06 - 33 - [plot data] 1. adc (lin/rin ? adc, ivol=0db) akm ak4691 lin/rin => adc thd+n vs. input level fs=48khz, fin=1khz -100 -70 -95 -90 -85 -80 -75 d b f s -120 +0 -100 -80 -60 -40 -20 dbr figure 19. thd+n vs. input level akm ak4691 lin/rin => adc thd+n vs. frequency fs=48khz, -1db input -100 -70 -95 -90 -85 -80 -75 d b f s 20 20k 50 100 200 500 1k 2k 5k 10k hz figure 20. thd+n vs. input frequency
[AKD4691-A] 2007/06 - 34 - akm ak4691 lin/rin => adc linearity fs=48khz, fin=1khz -120 +0 -100 -80 -60 -40 -20 d b f s -100 +0 -90 -80 -70 -60 -50 -40 -30 -20 -10 dbr figure 21. linearity akm ak4691 lin/rin => adc frequency response fs=48khz, -1db input -3 -0 -2.5 -2 -1.5 -1 -0.5 d b f s 20 20k 50 100 200 500 1k 2k 5k 10k hz figure 22. frequency response
[AKD4691-A] 2007/06 - 35 - akm ak4691 lin/rin => adc fft fs=48khz, fin=1khz, -1db input -140 +0 -120 -100 -80 -60 -40 -20 d b f s 20 20k 50 100 200 500 1k 2k 5k 10k hz figure 23. fft (1khz, -1dbfs) akm ak4691 lin/rin => adc fft fs=48khz, fin=1khz, -60db input -140 +0 -120 -100 -80 -60 -40 -20 d b f s 20 20k 50 100 200 500 1k 2k 5k 10k hz figure 24. fft (1khz, -60dbfs)
[AKD4691-A] 2007/06 - 36 - akm ak4691 lin/rin => adc fft fs=48khz, no signal -140 +0 -120 -100 -80 -60 -40 -20 d b f s 20 20k 50 100 200 500 1k 2k 5k 10k hz figure 25. fft (noise floor) akm ak4691 lin/rin => adc crosstalk fs=48khz, -1db input, blue:rch=>lch, red:lch=>rch 20 20k 50 100 200 500 1k 2k 5k 10k hz -140 -80 -130 -120 -110 -100 -90 d b tt t t tt t t tttt t figure 26. crosstalk
[AKD4691-A] 2007/06 - 37 - 2. adc (intl1/intr1 ? adc, intl2/intr2 ? adc, pre-amp gain=+24db, ivol=0db) akm ak4691 intl1/r1 => adc1, intl2/r2 => adc2 thd+n vs. input level fs=48khz, fin=1khz -100 +0 -90 -80 -70 -60 -50 -40 -30 -20 -10 dbr -100 -70 -95 -90 -85 -80 -75 d b f s figure 27. thd+n vs. input level akm ak4691 intl1/r1 => adc1, intl2/r2 => adc2 thd+n vs. frequency fs=48khz, -1db input 20 20k 50 100 200 500 1k 2k 5k 10k hz -100 -70 -95 -90 -85 -80 -75 d b f s figure 28. thd+n vs. input frequency
[AKD4691-A] 2007/06 - 38 - akm ak4691 intl1/r1 => adc1, intl2/r2 => adc2 linearity fs=48khz, fin=1khz -100 +0 -90 -80 -70 -60 -50 -40 -30 -20 -10 dbr -120 +0 -100 -80 -60 -40 -20 d b f s figure 29. linearity akm ak4691 intl1/r1 => adc1, intl2/r2 => adc2 frequency response fs=48khz, -1db input 20 20k 50 100 200 500 1k 2k 5k 10k hz -8 +0 -7 -6 -5 -4 -3 -2 -1 d b f s *positive input: c=1 f, ri=100k ? (ext hpf: fc=1.6hz); negative input: c=2.2 f, rn=2.2k ? (ext hpf: fc=33hz) figure 30. frequency response
[AKD4691-A] 2007/06 - 39 - akm ak4691 intl1/r1=>adc1, intl2/r2=>adc2 fft fs=48khz, fin=1khz, -1db input -140 +0 -120 -100 -80 -60 -40 -20 d b f s 20 20k 50 100 200 500 1k 2k 5k 10k hz figure 31. fft (1khz, -1dbfs) akm ak4691 intl1/r1=>adc1, intl2/r2=>adc2 fft fs=48khz, fin=1khz, -60db input -140 +0 -120 -100 -80 -60 -40 -20 d b f s 20 20k 50 100 200 500 1k 2k 5k 10k hz figure 32. fft (1khz, -60dbfs)
[AKD4691-A] 2007/06 - 40 - akm ak4691 intl1/r1=>adc1, intl2/r2=>adc2 fft fs=48khz, no signal -140 +0 -120 -100 -80 -60 -40 -20 d b f s 20 20k 50 100 200 500 1k 2k 5k 10k hz figure 33. fft (noise floor) akm ak4691 intl1/r1 => adc1, intl2/r2 => adc2 crosstalk fs=48khz, -1db input, blue:r1=>l1, red:l1=>r1, cyan:r2=>l2, magenta:l2=>r2 20 20k 50 100 200 500 1k 2k 5k 10k hz -140 -80 -130 -120 -110 -100 -90 d b tttttt t t t tt ttt t t t t tttttttt t t t ttttttttttt tt figure 34. crosstalk
[AKD4691-A] 2007/06 - 41 - 3. dac (dac ? lout/rout) akm ak4691 dac=>lineout thd+n vs. input level fs=48khz, fin=1khz -90 -60 -85 -80 -75 -70 -65 d b r a -120 +0 -100 -80 -60 -40 -20 dbfs figure 35. thd+n vs. input level akm ak4691 dac=>lineout thd+n vs. input frequency fs=48khz, 0dbfs input -90 -60 -85 -80 -75 -70 -65 d b r a 20 20k 50 100 200 500 1k 2k 5k 10k hz figure 36. thd+n vs. input frequency
[AKD4691-A] 2007/06 - 42 - akm ak4691 dac=>lineout linearity fs=48khz, fin=1khz -100 +0 -80 -60 -40 -20 d b r a -120 +0 -100 -80 -60 -40 -20 dbfs figure 37. linearity akm ak4691 dac=>lineout fequency response fs=48khz, 0dbfs input -2 +1 -1.5 -1 -0.5 -0 +0.5 d b r a 20 20k 50 100 200 500 1k 2k 5k 10k hz *line out: c=1 f, rseries=220 ? , rl=20k ? (ext hpf: fc=7.9hz) figure 38. frequency response
[AKD4691-A] 2007/06 - 43 - akm ak4691 dac=>lineout fft fs=48khz, fin=1khz, 0dbfs input -140 +0 -120 -100 -80 -60 -40 -20 d b r a 20 20k 50 100 200 500 1k 2k 5k 10k hz figure 39. fft (1khz, 0dbfs) akm ak4691 dac=>lineout fft fs=48khz, fin=1khz, -60dbfs input -140 +0 -120 -100 -80 -60 -40 -20 d b r a 20 20k 50 100 200 500 1k 2k 5k 10k hz figure 40. fft (1khz, -60dbfs)
[AKD4691-A] 2007/06 - 44 - akm ak4691 dac=>lineout fft fs=48khz, no signal -140 +0 -120 -100 -80 -60 -40 -20 d b r a 20 20k 50 100 200 500 1k 2k 5k 10k hz figure 41. fft (noise floor) akm ak4691 dac=>lineout crosstalk fs=48khz, blue:rch=>lch, red:lch=>rch -120 -70 -110 -100 -90 -80 d b 20 20k 50 100 200 500 1k 2k 5k 10k hz tttt t tt figure 42. crosstalk
[AKD4691-A] 2007/06 - 45 - 4. headphone (dac ? hpl/hpr) akm ak4691 dac=>hp thd+n vs. input level fs=48khz, fin=1khz -90 -60 -85 -80 -75 -70 -65 d b r a -120 +0 -100 -80 -60 -40 -20 dbfs figure 43. thd+n vs. input level akm ak4691 dac=>hp thd+n vs. input frequency fs=48khz, -3dbfs input -90 -40 -80 -70 -60 -50 d b r a 20 20k 50 100 200 500 1k 2k 5k 10k hz figure 44. thd+n vs. input fr equency (filter: 20khz aes17)
[AKD4691-A] 2007/06 - 46 - akm ak4691 dac=>hp linearity fs=48khz, fin=1khz -100 +0 -80 -60 -40 -20 d b r a -120 +0 -100 -80 -60 -40 -20 dbfs figure 45. linearity akm ak4691 dac=>hp fequency response fs=48khz, -3dbfs input -10 -2 -9 -8 -7 -6 -5 -4 -3 d b r a 20 20k 50 100 200 500 1k 2k 5k 10k hz *headphone out: c=220 f, rseries=6.8 ? , rl=16 ? (ext hpf: fc=31.7hz) figure 46. frequency response
[AKD4691-A] 2007/06 - 47 - akm ak4691 dac=>hp fft fs=48khz, fin=1khz, -3dbfs input -140 +0 -120 -100 -80 -60 -40 -20 d b r a 20 20k 50 100 200 500 1k 2k 5k 10k hz figure 47. fft (1khz, -3dbfs) akm ak4691 dac=>hp fft fs=48khz, fin=1khz, -60dbfs input -140 +0 -120 -100 -80 -60 -40 -20 d b r a 20 20k 50 100 200 500 1k 2k 5k 10k hz figure 48. fft (1khz, -60dbfs)
[AKD4691-A] 2007/06 - 48 - akm ak4691 dac=>hp fft fs=48khz, no signal -140 +0 -120 -100 -80 -60 -40 -20 d b r a 20 20k 50 100 200 500 1k 2k 5k 10k hz figure 49. fft (noise floor) akm ak4691 dac=>hp crosstalk fs=48khz, blue:rch=>lch, red:lch=>rch -100 -50 -90 -80 -70 -60 d b 20 20k 50 100 200 500 1k 2k 5k 10k hz figure 50. crosstalk
[AKD4691-A] 2007/06 - 49 - 4. speaker (dac ? spp/spn, spkg=+10.65db) akm ak4691 dac=>speaker(spkg=10.65db) thd+n vs. output power fs=48khz, fin=1khz 0 600m 100m 200m 300m 400m 500m w -70 -10 -60 -50 -40 -30 -20 d b -40 +0 -35 -30 -25 -20 -15 -10 -5 dbfs figure 51. thd+n vs. output power akm ak4691 dac=>speaker(spkg=10.65db) thd+n vs. input frequency fs=48khz, -3.75dbfs(po=240mw) -90 -50 -85 -80 -75 -70 -65 -60 -55 d b r a 20 20k 50 100 200 500 1k 2k 5k 10k hz figure 52. thd+n vs. input frequency
[AKD4691-A] 2007/06 - 50 - akm ak4691 dac=>speaker(spkg=10.65db) linearity fs=48khz, fin=1khz -100 +0 -90 -80 -70 -60 -50 -40 -30 -20 -10 d b r a -120 +0 -100 -80 -60 -40 -20 dbfs figure 53. linearity akm ak4691 dac=>speaker(spkg=10.65db) frequency response fs=48khz, -3.75dbfs input -4.75 -2.75 -4.5 -4.25 -4 -3.75 -3.5 -3.25 -3 d b r a 20 20k 50 100 200 500 1k 2k 5k 10k hz figure 54. frequency response
[AKD4691-A] 2007/06 - 51 - akm ak4691 dac=>speaker(spkg=10.65db) fft fs=48khz, fin=1khz, -3.75dbfs input -140 +0 -120 -100 -80 -60 -40 -20 d b r a 20 20k 50 100 200 500 1k 2k 5k 10k hz figure 55. fft (1khz, -3.75dbfs) akm ak4691 dac=>speaker(spkg=10.65db) fft fs=48khz, no signal -140 +0 -120 -100 -80 -60 -40 -20 d b r a 20 20k 50 100 200 500 1k 2k 5k 10k hz figure 56. fft (noise floor)
[AKD4691-A] 2007/06 - 52 - date (yy/mm/dd) manual revision board revision reason contents 07/06/14 km089100 0 first edition important notice z these products and their specifications are subject to change without notice. when you consider any use or application of these produc ts, please make inquiries the sales office of asahi kasei emd corporation (akemd) or authorized distributors as to current status of the products. z akemd assumes no liability for infringement of any patent, intellectual property, or other rights in the application or use of any information contained herein. z any export of these products, or devices or systems containi ng them, may require an export license or other official approval under the law and regulations of the country of e xport pertaining to customs and tariffs, currency exchange, or strategic materials. z akemd products are neither intended nor au thorized for use as critical components note1) in any safety, life support, or other hazard related device or system note2) , and akemd assumes no responsibility for such use, except for the use approved with the express written consent by representative director of akemd. as used here: note1) a critical component is one whose failure to func tion or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. note2) a hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fi elds, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. z it is the responsibility of the buyer or distributor of akemd pr oducts, who distributes, dis poses of, or otherwise places the product with a third party, to notify such third party in advance of the above cont ent and conditions, and the buyer or distributor agrees to assume any and all re sponsibility and liability for and hold akemd harmless from any and all claims arising from the use of said product in the absence of such notification. revision history
a a b b c c d d e e e e d d c c b b a a title size document number rev date: sheet of ak4691 0 akd4691-sub-57bga a3 11 friday, april 13, 2007 title size document number rev date: sheet of ak4691 0 akd4691-sub-57bga a3 11 friday, april 13, 2007 title size document number rev date: sheet of ak4691 0 akd4691-sub-57bga a3 11 friday, april 13, 2007 sdto1 sdto2 tp118 lin tp118 lin 1 tp113 gnd tp113 gnd 1 + c124 2.2u + c124 2.2u r107 51 r107 51 + c129 10u + c129 10u tp127 sdto tp127 sdto 1 r118 47k r118 47k r113 51 r113 51 r106 0 r106 0 r117 10k r117 10k c132 0.1u c132 0.1u + c108 1u + c108 1u r108 51 r108 51 u100 ak4691 u100 ak4691 lvdd g8 mutet h9 lvcm g9 rout f8 lout f9 beep e8 rin e9 lin d8 avdd d9 mrf a8 preln1 b8 prern2 a7 prern1 a6 mvdd b6 mpwr a5 intl1 b5 extl1 b4 intr2 a2 extr2 b1 tvdd1 c2 sdti d1 mcki d2 lrck f2 bick f1 tvdd2 h2 csn h3 cclk j3 cdti h4 mute j4 preln2 b7 sdto1 e1 sdto2 e2 pdn h5 spn j5 spp j6 svdd h6 vss1 c8 vcom c9 intl2 a4 extl2 b3 extr1 b2 intr1 a3 vss2 h1 dvdd g1 vss3 h7 hpr j7 hpl h8 vss4 j8 nc a9 nc a1 vcoc b9 nc c3 i2cn c1 mcko g2 nc j9 nc j2 nc j1 r112 51 r112 51 tp139 mcko tp139 mcko 1 + c102 1u + c102 1u + c118 1u + c118 1u tp134 pdn tp134 pdn 1 + c114 10u + c114 10u tp109 mutet tp109 mutet 1 tp123 dvdd tp123 dvdd 1 + c127 10u + c127 10u + c101 1u + c101 1u r110 (open) r110 (open) r104 1k r104 1k c128 0.1u c128 0.1u jp107 tvdd2 jp107 tvdd2 tp124 tvdd tp124 tvdd 1 + c116 2.2u + c116 2.2u + c104 1u + c104 1u c126 0.1u c126 0.1u r101 1k r101 1k c110 0.1u c110 0.1u jp109 i2c jp109 i2c c135 4700p c135 4700p tp110 vcom tp110 vcom 1 c113 0.1u c113 0.1u c136 (open) c136 (open) + c111 1u + c111 1u tp137 svdd tp137 svdd 1 + c121 2.2u + c121 2.2u tp133 mute tp133 mute 1 r115 51 r115 51 tp125 sdti tp125 sdti 1 tp116 lout tp116 lout 1 jp104 intr2 jp104 intr2 tp122 gnd tp122 gnd 1 jp101 intl1 jp101 intl1 tp121 mvdd tp121 mvdd 1 tp112 hpl tp112 hpl 1 cn102 12pin cn102 12pin 13 14 15 16 17 18 19 20 21 22 23 24 jp102 intl2 jp102 intl2 + c106 1u + c106 1u tp115 rout tp115 rout 1 r114 51 r114 51 r105 51 r105 51 cn103 12pin cn103 12pin 25 26 27 28 29 30 31 32 33 34 35 36 + c123 2.2u + c123 2.2u + c133 2.2u + c133 2.2u + c109 2.2u + c109 2.2u tp114 lvdd tp114 lvdd 1 tp120 avdd tp120 avdd 1 jp106 sdto-sel jp106 sdto-sel tp132 cdti tp132 cdti 1 tp130 csn tp130 csn 1 c117 0.1u c117 0.1u r111 51 r111 51 c115 0.1u c115 0.1u cn101 12pin cn101 12pin 1 2 3 4 5 6 7 8 9 10 11 12 jp108 mcko jp108 mcko tp119 beep tp119 beep 1 + c125 10u + c125 10u c134 0.1u c134 0.1u r103 1k r103 1k cn104 12pin cn104 12pin 37 38 39 40 41 42 43 44 45 46 47 48 + c112 2.2u + c112 2.2u + c122 2.2u + c122 2.2u tp136 spp tp136 spp 1 tp135 spn tp135 spn 1 tp126 mcki tp126 mcki 1 + c107 1u + c107 1u tp128 lrck tp128 lrck 1 jp103 intr1 jp103 intr1 r109 51 r109 51 c130 0.1u c130 0.1u r102 1k r102 1k tp111 hpr tp111 hpr 1 tp138 vcoc tp138 vcoc 1 tp117 rin tp117 rin 1 tp131 cclk tp131 cclk 1 + c103 1u + c103 1u tp129 bick tp129 bick 1 + c105 1u + c105 1u + c131 10u + c131 10u
a a b b c c d d e e e e d d c c b b a a lin beep lout rout rin avdd spp spn svdd extr2 intr1 intr2 extr1 extl2 intl1 intl2 extl1 hpl hpr csn cclk cdti mute pdn lvdd mcko mvdd lrck bick sdto mcki sdti tvdd dvdd title size document number rev date: sheet of ak4691 0 AKD4691-A a3 11 monday, april 23, 2007 title size document number rev date: sheet of ak4691 0 AKD4691-A a3 11 monday, april 23, 2007 title size document number rev date: sheet of ak4691 0 AKD4691-A a3 11 monday, april 23, 2007 cn3 12pin cn3 12pin 25 26 27 28 29 30 31 32 33 34 35 36 cn2 12pin cn2 12pin 13 14 15 16 17 18 19 20 21 22 23 24 cn1 12pin cn1 12pin 1 2 3 4 5 6 7 8 9 10 11 12 cn4 12pin cn4 12pin 37 38 39 40 41 42 43 44 45 46 47 48
a a b b c c d d e e e e d d c c b b a a beep hpr hpl lout rout intl2 extl2 extl1 intl1 spp spn d3v tvdd dvdd svdd avdd vcc lvdd extr1 intr1 extr2 intr2 rin lin beep mvdd title size document number rev date: sheet of power supply, i/o 0 AKD4691-A a3 25 monday, may 21, 2007 title size document number rev date: sheet of power supply, i/o 0 AKD4691-A a3 25 monday, may 21, 2007 title size document number rev date: sheet of power supply, i/o 0 AKD4691-A a3 25 monday, may 21, 2007 hp rca hp rca intl2 extl2 rca rca 3.5st 3.5st intl1 extl1 intr1 extr1 intr2 extr2 r2 (open) r2 (open) r16 20k r16 20k avdd1 t45-or avdd1 t45-or 1 5v1 t45-red 5v1 t45-red 1 l5 (short) l5 (short) 1 2 r3 (short) r3 (short) j8 hpr j8 hpr 1 2 3 4 5 j1 mic1/beep j1 mic1/beep 4 6 3 l3 (short) l3 (short) 1 2 + c10 47u + c10 47u 1 2 + c24 47u + c24 47u 1 2 j5 lout j5 lout 1 2 3 4 5 jp1 gnd jp1 gnd jp4 avdd-sel jp4 avdd-sel l8 (short) l8 (short) 1 2 + c27 47u + c27 47u 1 2 l4 (short) l4 (short) 1 2 + c13 1u + c13 1u r23 20k r23 20k l2 (short) l2 (short) 1 2 mvdd1 t45-or mvdd1 t45-or 1 dgnd1 t45-bk dgnd1 t45-bk 1 jp3 svdd-sel jp3 svdd-sel j3 lin/rin j3 lin/rin 4 6 3 c21 0.1u c21 0.1u d3v1 t45-or d3v1 t45-or 1 svdd1 t45-or svdd1 t45-or 1 l1 (short) l1 (short) 1 2 jp6 tvdd-sel jp6 tvdd-sel jp27 l1-sel jp27 l1-sel r14 20k r14 20k + c34 1u + c34 1u + c36 220u + c36 220u jp2 reg jp2 reg r1 (short) r1 (short) r13 220 r13 220 jp12 hpl jp12 hpl r4 (open) r4 (open) c22 0.1u c22 0.1u vcc1 t45-or vcc1 t45-or 1 jp10 lout-sel jp10 lout-sel r19 (short) r19 (short) + c28 47u + c28 47u 1 2 agnd1 t45-bk agnd1 t45-bk 1 j10 spk j10 spk 4 6 3 jp5 dvdd-sel jp5 dvdd-sel jp8 mvdd-sel jp8 mvdd-sel jp7 vcc-sel jp7 vcc-sel j2 mic2 j2 mic2 4 6 3 jp11 rout-sel jp11 rout-sel + c33 1u + c33 1u j9 hp/line j9 hp/line 6 4 3 c15 0.22u c15 0.22u j6 rout j6 rout 1 2 3 4 5 t1 ta48030f t1 ta48030f in out gnd + c14 1u + c14 1u r22 10 r22 10 j7 hpl j7 hpl 1 2 3 4 5 + c29 47u + c29 47u 1 2 r17 (short) r17 (short) + c35 220u + c35 220u r21 10 r21 10 jp13 hpr jp13 hpr jp29 l2-sel jp29 l2-sel r15 220 r15 220 l6 (short) l6 (short) 1 2 jp26 spk jp26 spk r9 10 r9 10 jp30 r2-sel jp30 r2-sel r18 16 r18 16 dvdd1 t45-or dvdd1 t45-or 1 l9 (short) l9 (short) 1 2 tvdd1 t45-or tvdd1 t45-or 1 + c23 47u + c23 47u 1 2 jp28 r1-sel jp28 r1-sel + c25 47u + c25 47u 1 2 c16 0.22u c16 0.22u + c11 47u + c11 47u 1 2 r20 16 r20 16 + c12 1u + c12 1u + c26 47u + c26 47u 1 2
a a b b c c d d e e e e d d c c b b a a xtl ext-mclk 4114-mcko ext-bick 4114-bick 4114-pdn ext-mcko 4114-int0 d3v ext-lrck 4114-lrck pdni title size document number rev date: sheet of clock 0 AKD4691-A a3 35 monday, may 21, 2007 title size document number rev date: sheet of clock 0 AKD4691-A a3 35 monday, may 21, 2007 title size document number rev date: sheet of clock 0 AKD4691-A a3 35 monday, may 21, 2007 ext dir 1024fs 64fs 512fs 256fs dir 4040 h l thr inv mcko 4040 dir 32fs fs l c44 0.1u c44 0.1u d1 hsu119 d1 hsu119 k a c43 0.1u c43 0.1u r26 1k r26 1k j11 ext j11 ext 1 2 3 4 5 u5 74hcu04 u5 74hcu04 1a 1 1y 2 2a 3 2y 4 3a 5 3y 6 vcc 14 gnd 7 4y 8 4a 9 5y 10 5a 11 6y 12 6a 13 r5 1m r5 1m jp31 xte jp31 xte r24 51 r24 51 r8 10k r8 10k d2 hsu119 d2 hsu119 k a jp16 mkfs jp16 mkfs c39 0.1u c39 0.1u c42 0.1u c42 0.1u jp18 bick-sel jp18 bick-sel x2 11.2896mhz x2 11.2896mhz 1 2 r25 10k r25 10k jp15 mclk jp15 mclk jp19 phase jp19 phase jp14 ext jp14 ext c37 5p c37 5p sw1 pdn sw1 pdn 2 1 3 u6 74hc4040 u6 74hc4040 clk 10 rst 11 q1 9 q2 7 q3 6 q4 5 q5 3 q6 2 q7 4 q8 13 q9 12 q10 14 q11 15 q12 1 vd 16 dgnd 8 u7 74hc14 u7 74hc14 1a 1 1y 2 2a 3 2y 4 3a 5 3y 6 vcc 14 gnd 7 4y 8 4a 9 5y 10 5a 11 6y 12 6a 13 sw2 dir sw2 dir 2 1 3 c40 0.1u c40 0.1u jp17 bgfs jp17 bgfs c38 5p c38 5p c19 0.1u c19 0.1u jp21 lrck-sel jp21 lrck-sel u3 74ac74 u3 74ac74 1clr 1 1d 2 1ck 3 1pr 4 1q 5 1q 6 vcc 14 gnd 7 2clr 13 2d 12 2ck 11 2pr 10 2q 9 2q 8 led1 erf led1 erf k a
a a b b c c d d e e e e d d c c b b a a 4114-sdto 4114-bick 4114-lrck 4114-mcko cad0 mutei mcko 4114-pdn daux d3v 4114-int0 title size document number rev date: sheet of dir/dit 0 AKD4691-A a3 45 monday, may 21, 2007 title size document number rev date: sheet of dir/dit 0 AKD4691-A a3 45 monday, may 21, 2007 title size document number rev date: sheet of dir/dit 0 AKD4691-A a3 45 monday, may 21, 2007 dif0 dif2 ocks1 cad0 mute dif1 h l port2 totx141 port2 totx141 gnd 1 vcc 2 in 3 r39 100k r39 100k c56 0.47u c56 0.47u c45 0.1u c45 0.1u l7 (short) l7 (short) 1 2 r37 100k r37 100k + c48 10u + c48 10u c52 5p c52 5p c55 0.1u c55 0.1u jp22 4114-mcki jp22 4114-mcki c49 0.1u c49 0.1u c51 0.1u c51 0.1u + c54 10u + c54 10u c46 0.1u c46 0.1u x1 12.288mhz x1 12.288mhz 1 2 ------off------ 1234 56 s1 sw dip-6 ------off------ 1234 56 s1 sw dip-6 1 2 3 4 5 6 7 8 9 12 10 11 c53 5p c53 5p port1 torx141 port1 torx141 out 1 vcc 3 gnd 2 r27 470 r27 470 c47 0.1u c47 0.1u rp1 47k rp1 47k 7 6 5 4 3 2 1 u8 ak4114 u8 ak4114 ips0 1 nc 2 dif0 3 test2 4 dif1 5 nc 6 dif2 7 ips1 8 p/sn 9 xtl0 10 xtl1 11 tvdd 13 dvss 14 tx0 15 tx1 16 bout 17 cout 18 uout 19 vout 20 dvdd 21 dvss 22 mcko1 23 bick 26 mcko2 27 daux 28 xto 29 xti 30 pdn 31 cm0 32 cm1 33 ocks1 34 ocks0 35 int0 36 avdd 38 r 39 vcom 40 avss 41 rx0 42 nc 43 rx1 44 test1 45 rx2 46 nc 47 rx3 48 vin 12 lrck 24 sdto 25 int1 37 + c50 10u + c50 10u r38 100k r38 100k r28 18k r28 18k
a a b b c c d d e e e e d d c c b b a a lrck bick mcko cad0 sdto daux ext-mcko vcc cdti ext-mclk ext-bick ext-lrck d3v 4114-sdto cclk csn mcki sdti pdn pdni mutei mute title size document number rev date: sheet of logic 0 AKD4691-A a3 55 tuesday, may 29, 2007 title size document number rev date: sheet of logic 0 AKD4691-A a3 55 tuesday, may 29, 2007 title size document number rev date: sheet of logic 0 AKD4691-A a3 55 tuesday, may 29, 2007 cclk/sci cdto/sda(ack) cdti/sda csn lrck mclk vcc sdti bick 3-wire i2c slave master adc dir gnd gnd sdto r29 10k r29 10k u11 74avc8t245 u11 74avc8t245 a1 3 a2 4 a3 5 a4 6 a5 7 a6 8 a7 9 a8 10 b1 21 b2 20 b3 19 b4 18 b5 17 b6 16 b7 15 b8 14 gnd 11 gnd 12 gnd 13 vcca 1 dir 2 vccb 24 vccb 23 oe 22 r31 10k r31 10k c60 0.1u c60 0.1u c58 0.1u c58 0.1u c63 0.1u c63 0.1u r35 470 r35 470 rp2 47k rp2 47k 7 6 5 4 3 2 1 r42 51 r42 51 r32 10k r32 10k c62 0.1u c62 0.1u port4 ctrl port4 ctrl 1 3 5 7 9 10 8 6 4 2 c57 0.1u c57 0.1u r36 1k r36 1k jp25 ctrl-sel jp25 ctrl-sel u12 74lvc07 u12 74lvc07 1a 1 2a 3 3a 5 4a 9 5a 11 6a 13 vcc 14 gnd 7 1y 2 2y 4 3y 6 4y 8 5y 10 6y 12 port3 dsp port3 dsp 1 3 5 7 9 10 8 6 4 2 r40 51 r40 51 u9 74avc8t245 u9 74avc8t245 a1 3 a2 4 a3 5 a4 6 a5 7 a6 8 a7 9 a8 10 b1 21 b2 20 b3 19 b4 18 b5 17 b6 16 b7 15 b8 14 gnd 11 gnd 12 gnd 13 vcca 1 dir 2 vccb 24 vccb 23 oe 22 r30 10k r30 10k r33 470 r33 470 r41 51 r41 51 r44 51 r44 51 u10 74avc8t245 u10 74avc8t245 a1 3 a2 4 a3 5 a4 6 a5 7 a6 8 a7 9 a8 10 b1 21 b2 20 b3 19 b4 18 b5 17 b6 16 b7 15 b8 14 gnd 11 gnd 12 gnd 13 vcca 1 dir 2 vccb 24 vccb 23 oe 22 r45 51 r45 51 r34 470 r34 470 rp3 47k rp3 47k 7 6 5 4 3 2 1 c61 0.1u c61 0.1u c59 0.1u c59 0.1u jp24 sdti-sel jp24 sdti-sel jp23 m/s jp23 m/s r43 51 r43 51
|
